Electronic devices such as computers and televisions incorporate within there operating structure semiconductor devices such as diodes or transistors. Such semiconductor devices may be manufactured through a series of processes of forming a film on a wafer. The semiconductor wafer may be created by growing silicon oxide and implanting impurity ions into required portions of the silicon dioxide film to electrically activate the portions and then connecting wirings between the portions.
As a result of an increase in the integration density of semiconductor devices, it may prove difficult to drive semiconductor devices using one metal wiring layer. Accordingly, the development and use of multilayer semiconductor devices has become prevalent. An interlayer insulating layer is formed between conducting layers of a multilayer semiconductor device in order to provide insulation between the conducting layers. In order to electrically connect the stacked conducting layers, it may be necessary to perform a separate contact process in which contact holes are formed in the interlayer insulating layer and the contact holes subsequently filled with a electrically conducting material. A reduction in size of the semiconductor device and the line width has may become essential in addition to an increase in the integration density of semiconductor devices. Accordingly, technologies for implementing fine line widths have become important in the fabrication of semiconductor devices. There are many limitations and difficulties when patterning narrower lines and smaller contact holes.
As illustrated in example FIG. 1, interlayer insulating layer 103 is deposited on and/or over lower metal wiring 101. Diffusion barrier layer 102 and capping layer 104 are deposited on and/or over interlayer insulating layer 103 to prevent diffusion of fluorine (F) into interlayer insulating layer 103. To form contact vias, a photoresist material is coated on capping layer 104 and then selectively exposed to light, developed, and patterned. To form contact holes, capping layer 104 and interlayer insulating layer 103 may be etched the patterned photoresist layer as an etch mask. The etching process may utilize a reactive ion etching (RIE) method.
A plasma treatment process is performed to remove a metal organic polymer remaining in the contact vias after RIE. The plasma treatment process may cause tapering at both-side edges of capping layer 104 at upper portions of the contact vias. Chemical mechanical polishing (CMP) may be conducted upon forming contacts 105 by filling tungsten (W) into the gaps of the contact vias with the tapered side edges of capping layer 104. Tungsten bridge “A” may occur depending on the distance between contacts 105. Especially, if the design rule is small such that the contact vias have a small margin between them, a tungsten bridge phenomenon becomes more serious due to tapering of the upper profiles of the contact vias.